CoE 243 Sequential Circuits Lab (Latches & Flip Flops)

Purpose:

1. Become Familiar with:

    SR Latch

    Transparent D Latch (7475)

    D Flip Flop (7474)

    JK Flip Flop (7473, 7476, 74107, 74109, or 74113)

3. Be able to get needed information from a data book.

4. Be able to read and implement a function table.

Procedure:

Part1

Construct an SR Latch, using NAND gates and prove its Function Table.

Connect a Transparent D Latch and prove its Function Table.

Determine the minimum allowable pulse width of the Enable input of the 7475 D Latch.  (Use the data sheet.)

Part 2

Connect a JK Flip Flop and prove its Function Table.

Connect a D Flip Flop and prove its Function Table.

Determine the minimum allowable pulse width of the Clock input of the D FF and JK FF.  (Use the data sheet.)

Look up the "Set Up Time", "Hold Time", "Propagation Delay", and "Maximum Clock Frequency" of the JK Flip Flop. Why is it important to know this information? (You may have to do some reading to answer this.)