CS 245 Sequential Logic Design

Purpose: 

1. Get more practice with reducing Boolean equations.

2. Use D Flip Flops and JK Flip Flops in a sequential circuit.

3. Be able to implement a synchronous counter.

4. Use CircuitMaker or Digital Works to design and simulate a sequential circuit.

Procedure:

1. Design a 3 bit synchronous counter, with the count sequence below, using D flip-flops.

2. Design a 3 bit synchronous counter, with the count sequence below, using JK flip-flops.

3. Implement the most efficient of the two counter designs with CircuitMaker or Digital Works. 

Count Sequence:

0 -> 1 -> 3 -> 2 -> 6 -> 7 -> 5 -> 4 -> 0

Questions:

What are some uses for these circuits?

Do either D flip-flops or JK flip-flops have an advantage over the other in this application? Why or why not?

This count sequence has the advantage of being "glitch-proof" (it never, even briefly, goes to the wrong state). Can you see anything about it that might be the reason? Hint: What is special about the gray code, and why is it used? Why might a "glitch-proof" count sequence be necessary?

What are some advantages of synchronous counters over asynchronous counters?

What are some limitations of synchronous counters?