Rex N. Fisher  --  CS 245: Course Outline

This page was last updated on 09/21/04


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IMPORTANT: Schedules, assignments, and policies are subject to change. You will be given advance notification of any changes.


Day 1:    Course Introduction
               Overview of Computer Evolution
               Overview of Computer Organization, Operation and Construction
               Pretest
               READ: Course Information (Handouts, Web Page, etc.)
               HW1: Download & Install CircuitMaker (or Digital Works), and CUPL

Day 2:    Review Combinational Logic
                    Logic Gates
                    Boolean Algebra
                    K-Maps
                    Circuit Design/Analysis
                    Multiplexers
                    Encoders
                    Decoders
               READ: Chapt 1.1 thru 1.4
               HW2: Handout: Combinational Logic Design

Day 3:    Review Sequential Logic
                    Clocks
                    Latches
                    Flip Flops
                    Memory
                    Counters
                    Shift Registers
               READ: Chapt 1.5 thru 1.8
               HW3: Handout: Sequential Logic Design

Day 4:    Review Finite State Machine Design
                    Moore Machines
                    Mealy Machines
                    FSM Implementation
               READ: Chapt 2.1 thru 2.6
               HW4: Handout: State Machine Design

Day 5:    Instruction Set Architectures
                    Assemblers
                    Linkers
                    Compilers
                    Instruction Types
                    Data Types
                    Addressing Modes
                    Instruction Formats
                    Register Transfer Language
                    Instruction Set Design
               READ: Chapt 3.1 thru 3.6, Chapt 5.1 & 5.2
               TAKE-HOME TEST 1 (Due on Day 6)

Day 6:     Introduction to Computer Organization
                    System Busses
                    Instruction Cycles
                    CPUs
                    Memory Subsystems
                    I/O Subsystems
               READ: Chapt 4.1 thru 4.7
               HW6: Begin working on the the CPU Project (Very Simple CPU).

Day 7:     CPU Design
                    Specifications
                    Operation
                    Registers
                    Data Path
                    Control Unit
               READ: Chapt 6.1 thru 6.6
               HW7: Continue working on the CPU Project.

Day 8:     Hardwired Controllers ("Lab Class")
                    Implement a simple state machine controller for the Very Simple CPU with PLDs 
               HW8: Continue working on the CPU Project.          

Day 9:     Microsequencer Control Unit Design
                    Operation
                    Microinstructions
                    Designing the Hardware & Microcode
                    Microprogrammed Control vs Hardwired Control
               READ: Chapt 7.1 thru 7.7
               HW9: Continue working on the CPU Project.             

Day 10:   Microprogrammed (ROM) Controllers ("Lab Class")
                    Implement a simple microsequencer controller for the Very Simple CPU
               TAKE-HOME TEST 2 (Due on Day 11)   

Day 11    Computer Arithmetic
                    Base Conversions
                    Signed & Unsigned Numbers
                    Binary Addition
                    Binary Subtraction
                    Logical Operations
                    ALU Design
               READ: Chapt 8.1 thru 8.7
               HW11: Handout: Design a Simple ALU 
                           Continue working on the CPU Project.                

Day 12:   Memory Organization
                    Main Memory
                    Magnetic Memory
                    Cache Memory
                    Virtual Memory
               READ: Chapt 9.1 thru 9.6
               HW12: Continue working on the CPU Project. 

Day 13:   Input/Output
                    Data Transfers
                    Programmed I/O
                    Interrupts
                    Direct Memory Access
                    Serial Communication
               READ: Chapt 10.1 thru 10.8
               HW13: Continue working on the CPU Project. 

Day 14:   Project ("Lab Class")
                    Burn PLDs
                    Troubleshooting
                    Final Assembly/Design Details
               HW14: Finish CPU Project. 

Day 15:   Project Presentations
               Class/Teacher Evaluations
               TAKE-HOME FINAL TEST (Due on Day 16)

Day 16:   Project Presentations
               Review Final Test